Semiconductor Test Engineering Team Leader

• 8+ years in semiconductor test engineering, including leadership or technical lead roles.
• Deep experience with ATE test development (e.g., Advantest 93K, Teradyne).
• Strong understanding of DFT (scan, ATPG, LBIST, MBIST), memory testing, and high-speed interface testing.
• Experience managing external test development partners or OSATs.
• Proven ability to lead and mentor test engineering teams.
• Solid background in advanced CMOS nodes and familiarity with advanced packaging test challenges.
• Expertise in silicon debug, characterization, and correlation across ATE and system-level environments.
• Ability to collaborate across design, architecture, product engineering, packaging, and operations..

• Experience with AI/ML accelerator chips or other high-performance compute ICs.
• Prior involvement with PCIe Gen5/Gen6 or LPDDR4/5/6 test methodologies.
• Familiarity with signal-integrity-aware test development and high-speed IO margining.
• Experience with chiplets, 2.5D/3D IC test flows, or heterogeneous integration.

• Competitive salary: A competitive salary reflective of your experience and the specialist nature of the role.
• Equity & Ownership: meaningful equity so everyone shares in the value creation
• Benefits: Private Medical, Dental and Vision, Contributory Pension, 25 Days holiday plus bank holidays and Life/Critical Illness Insurance.

Our work involves technologies subject to UK, US and other international export control regulations. Certain roles may require additional eligibility checks to ensure compliance with applicable law. We'll be transparent about this throughout the hiring process.

We are seeking a senior Semiconductor Test Engineering leader to drive manufacturing test strategy and silicon production readiness for next-generation AI accelerator devices. This role combines deep technical expertise in high-performance compute silicon with leadership responsibility for internal product engineering teams and external development partners. The successful candidate will oversee all aspects of production test development - from DFT strategy and ATE bring-up through silicon characterisation, yield optimisation, advanced packaging test, and high-volume manufacturing ramp - ensuring robust, scalable, and cost-effective test solutions for advanced AI accelerator platforms.

• Drive the manufacturing test strategy for an AI accelerator chip featuring PCIe Gen6, LPDDR, advanced CMOS nodes, and advanced packaging (e.g., 2.5D/3D, chiplet).
• Lead and manage a team of chip test engineers responsible for test planning, test program development, pattern bring-up, silicon characterization, debug, and optimization.
• Manage subcontracted test development partners (OSATs, ATE vendors, external engineering services). Includes scoping, technical oversight, schedule tracking, and quality control of deliverables.
• Define and drive test software architecture, DFT usage, and test pattern development strategies for high-speed logic, SRAM, DRAM, and High Speed IO blocks.
• Work closely with design, DFT, product engineering, packaging, and validation teams to ensure robust test coverage, manufacturability, and yield ramp success.
• Oversee test development for high speed interfaces such as PCIe Gen6 and multi-GHz LPDDR.
• Guide development of structural and functional test content (scan, MBIST, JTAG, HSIO tests, system-level tests).
• Lead silicon bring-up and development on ATE: correlation, failure analysis, shmooing, corner testing, stress testing, and yield improvement activities.
• Define KPIs and metrics for subcontractor performance, test coverage, yield, time-to-test, and cost optimization.
• Drive continuous improvement in test methodologies, automation, data analytics, and debug infrastructure.
• Ensure robust test flows for advanced packaging (thermals, interposer/bridge connections, TSV integrity, die-to-die IO testing).
• Support qualification, reliability testing, and high-volume manufacturing transfer.

• Ownership and execution: you will have full agency to drive your work forward
• Rapid iteration: we all work directly with top leadership to move from idea to hardware on ambitious timelines
• Full-stack engagement: hardware, software, silicon, and modelling teams all work closely together to create a product with generational impact
• Optimistic and pragmatic: we possess the will to win, and to do the hard work to get us there
• Team player mentality: the mission is bigger than any of us, and we have the curiosity and technical focus to see the best idea shipped, no matter who's it is