Computing Researcher

• Strong technical background with a profound understanding of one or more of the following: memory, interconnect, cluster computing, HPC servers, AI servers, CPU/GPU/NPU/DPU, accelerators, and hardware/software co-design.
• Extensive industry experience in workload modeling and CPU/NPU architecture development.
• Quick learner, capable of familiarizing oneself with new areas through academic research, conferences, and discussions with experts.
• Strong technical insight and broad ICT knowledge, with awareness of emerging technologies.
• Excellent interpersonal skills and experience engaging with reputable companies and individuals; able to present ideas clearly to diverse audiences.
• Master's or PhD degree in Computer Science, Electrical Engineering, or Computer Engineering, with strong expertise in computer architecture, HPC, AI, and networking.
• Solid track record of scientific publications in leading conferences.

• Fluent in English (spoken and written); native Chinese speaker is a plus.

We are looking for a Computing Hardware and Software Co-design Researcher with expertise in CPU and NPU architectures and a focus on performance workload modeling. The ideal candidate will be a technical expert in the compute domain, responsible for integrating hardware and software solutions. This role also includes supporting the local research team in communicating effectively with the headquarter in China, ensuring seamless collaboration. Strong analytical skills, proficiency in relevant programming languages, and a passion for innovative co-design methodologies are essential.

• This expert will be a key member of a team at the forefront of CPU/NPU development. Responsibilities will include planning and implementing tool systems for architectural exploration and performance analysis. Additionally, the role involves driving software/hardware vertical integration and planning software/hardware co-optimization features for next-generation processors.
• The ideal candidate should possess a strong understanding of CPU/NPU architecture and workload extraction, as well as a good grasp of compiler, binary analysis, and software/hardware co-optimization.