Hardware Verification Engineer

• BS, MS in Electrical Engineering, Computer Engineering or Computer Science

• 8+ years and current hands-on experience in block-level/IP-level/SoC-level verification

• Proficiency in Verilog, SystemVerilog

• Familiarity with industry-standard EDA tools for simulation and debug

• Deep experience with UVM-based testbenches

• Knowledge of Arm AMBA protocols such as AXI, APB, and AHB

• Experience on working with IP's for caches, cache coherency, memory subsystems, interconnects, and NoC's

• Excellent problem-solving skills and attention to detail

• Strong communication and collaboration skills

• Experience with modern programming languages like Python

• Understanding of Arm CHI protocol is a plus

• Experience with formal verification techniques, emulation platforms is a plus

• Salary commensurate with experience
• Performance incentives
• Comprehensive medical, dental, and vision benefits
• 401(k) retirement plan
• Equity

Baya Systems is inspired by the baya bird, also known as the weaver. Baya birds weave very unique and intricate hanging nests from different materials. The nests are robust and safe while being extremely lightweight and efficient.

Baya is a fast-moving Series B startup built by serial entrepreneurs with a vision to accelerate intelligent computing in the emerging chiplet era. We focus on software-driven, unified fabric solutions for single-die and multi-die systems. We design and license disruptive intellectual property for use in semiconductor chips, with software development platforms to simplify the design process and reduce the time to market for complex System-on-Chip (SoC) and multi-chiplet systems. This enables our partners to innovate and deliver compelling solutions for data center, infrastructure, AI, Automotive, and Edge IoT markets. We are looking for energetic and dedicated individuals share our passion for enabling innovation and excellence in the semiconductor industry that empowers game-changing products and services!

We are seeking a seasoned Design Verification designer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions

Responsibilities:

• Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems

• Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards

• Collaborate with software teams to define and implement configurable testbenches

• Work with design teams test plans, failure debug, coverage, etc.

England, UK (Bristol, Cambridge, London)

Qualifications and Preferred Skills